`include "define.svh"

module register (
    input wire						        clk,
    //write register
    input wire                              wen_i,
    input wire [`REG_ADDR_WIDTH - 1 : 0]	waddr_i,
    input wire [`REG_WIDTH - 1 : 0]			wdata_i,
    //read register 1
    input wire [`REG_ADDR_WIDTH - 1 : 0]	raddr1_i,
    output reg [`REG_WIDTH - 1 : 0]			rdata1_o,
    //read register 2
    input wire [`REG_ADDR_WIDTH - 1 : 0]	raddr2_i,
    output reg [`REG_WIDTH - 1 : 0]			rdata2_o
);

	reg [`REG_WIDTH - 1 : 0] regs [31 : 0];     // 32 registers
	// Write register.
    always_ff @( posedge clk )
        // Delete the special judgment on the ZERO REGISTER
		if ( wen_i == `true ) 				regs[waddr_i] <= wdata_i;
	// Read Register 1
	always_comb
		// Special judgment on the ZERO REGISTER
		if ( raddr1_i == `ZERO_REG_ADDR )		rdata1_o = `ZERO_REG;
		else 									rdata1_o = regs[raddr1_i];
	// Read Register 2
	always_comb
		// Special judgment on the ZERO REGISTER
		if ( raddr2_i == `ZERO_REG_ADDR )		rdata2_o = `ZERO_REG;
		else 									rdata2_o = regs[raddr2_i];

endmodule